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ZXFV4089
VIDEO AMPLIFIER WITH DC RESTORATION
DEVICE DESCRIPTION
The ZXFV4089 is a DC restoring circuit and low-distortion video amplifier. It is specially designed to provide brightness level stability as a `black-level clamp' in video systems with very low distortion and low power consumption. A high fidelity video amplifier is combined with a sample-hold switch circuit using an external coupling capacitor to provide level-shifting of the video output such that a time-gated sample of the waveform is set to be equal to an external reference voltage (usually zero voltage). A buffered TTL/CMOS logic input signal controls the switch. The gain is set externally by two resistors. In a typical application, the sample-hold circuit is gated on during part of the back-porch interval of an analog video waveform. Then the video waveform is stabilised for the remainder of the line-scan interval.
FEATURES AND BENEFITS
* Various TV systems, PAL, NTSC, SECAM * Buffered output using high quality video amplifier * Gain is set using two external resistors * On chip sample/hold capacitor * 300 MHz bandwidth * 0.02% differential gain * 0.02 differential phase * +/-5V supply operation * 8 mA supply current * Pin and function compatible with industry
standard part
APPLICATIONS ORDERING INFORMATION
Part Number
ZXFV4089N8TA ZXFV4089N8TC
Container
Reel 7 Reel 13
Increment
500 2500
* Black Level Clamp, providing stable intensity in
video systems such as cameras image capture video mixing displays
* DC restoration of other high frequency signals
CONNECTION DIAGRAM
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002 1
ZXFV4089
ABSOLUTE MAXIMUM RATINGS
Positive Supply voltage VCC to GND Negative Supply Voltage VEE to GND Input voltage, pins 1,2,3 to GND Output current, pin 7 Current into Vin and HOLD, pins 2 & 4 Operating Temperature Range Operating Ambient Junction temperature TJMAX -0.5V to +5.5V -5.5V to +0.5V VEE -0.5V to VCC +0.5V 60mA 5mA -40 C to 85 C Storage -65 C to +150 C 150 C**
**The thermal resistance from the semiconductor die to ambient is typically 120 C/W when the SO16 package is mounted on a PCB in free air. The power dissipation of the device when loaded must be designed to keep the device junction temperature below TJMAX. *During power-up and power-down, these voltage ratings require that signals be applied only when the power supply is connected.
ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = -5V, RF and RG = 1k , RLOAD = 1k, Tamb = 25 C unless otherwise stated.
PARAMETER DC characteristics V CC Supply current, holding V CC Supply current, sampling V EE Supply current, holding V EE Supply current, sampling Amplifier section Input offset voltage + input bias current - input bias current Transimpedance + input resistance Open loop gain Output voltage swing Output drive current Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Common mode input voltage range Amplifier output voltage swing Restore section Composite Input Offset Voltage, from V REF HOLD = LOW to amplifier output V REF input bias current Input restore current available, pin 2 HOLD = LOW HOLD = LOW P P P 180 3 3 300 7 12 mV A A HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH HOLD = HIGH P P P P P P P P P P C P 2.5 500 1.5 48 2.5 40 49 51 57 58 3 3.5 1 5 5 1800 2 61 3.0 10 10 10 mV A A K M dB V mA dB dB V V HOLD = HIGH HOLD = LOW HOLD = HIGH HOLD = LOW P P P P 8 8.5 8 8.5 10 11 10 11 mA mA mA mA CONDITIONS P/C MIN TYP MAX UNIT
TEST - P = 100% production tested, C = characterised
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002 2
ZXFV4089
ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = -5V, RF and RG = 1k , RLOAD = 1k, Tamb = 25 C unless otherwise stated.
PARAMETER V REF input voltage range Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Logic input HIGH V Hmin Logic input LOW V Lmax HOLD = LOW HOLD = HIGH Logic input Low current, I IL Logic input High current, I IH AC characteristics Amplifier section Slew Rate Bandwidth, -3dB Bandwidth, 0.1dB Differential Gain, NTSC HOLD = HIGH, 2V pk-pk HOLD = HIGH HOLD = HIGH HOLD = HIGH, f = 3.58 MHz, 280mV pk-pk, DC = -714 to +714 mV HOLD = HIGH, f = 3.58 MHz, 280mV pk-pk, DC = -714 to +714 mV C C C C 400 300 100 0.02 V/s MHz MHz % CONDITIONS HOLD = LOW HOLD = LOW HOLD = LOW P/C C P P P P P P 0.8 40 12 100 60 60 MIN TYP 2 90 90 2 MAX UNIT V dB dB V V A A
R f = R g = 1k ohms, R LOAD = 150 ohms, C LOAD = 10 pF
Differential Phase, NTSC
C
0.02
deg
Restore section Slew rate Time to enable Hold Time to disable Hold HOLD = LOW C C C 25 25 40 V/s ns ns
TEST - P = 100% production tested, C = characterised
1. The logic conditions for DC characteristics are: logic LOW = 0.8V max, logic HIGH = 2V min.
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002 3
ZXFV4089
ZXFV4089DETAILED OPERATING NOTES
Introduction This device provides a video feed-back amplifier together with a sample-hold system to allow DC restoration. The Connection Diagram on page 1 shows a typical video signal application. No output termination is shown in the diagram, but if desired the output can drive a 75 ohm cable via a 75 ohm series terminating resistor. Amplifier configuration The amplifier configuration uses high gain with feedback in a non-inverting configuration. Two external resistors are required to set the gain. The restoration voltage is set by an external reference, Vref, normally ground. The input signal is applied via an external input coupling capacitor which is used to store a DC control level when the sample-hold switch is open. When the switch is closed, the stored level is driven to a new value by an external sampling pulse. DC restoration HOLD is a TTL input signal which is buffered and controls the sample-hold switch. A logic LOW state closes the switch and so enables the feedback control loop to set the output level equal to Vref (usually ground). The level of DC shift is maintained when the logic control returns to the HIGH state and the switch opens. In this way the whole waveform is conditionally level shifted, or `restored' to the new DC level. The sample-hold loop contains the video feed-back amplifier within its path, and also includes an additional sample-hold sense amplifier which compares Vref with the output voltage using an internal low-pass filter. In the high state, the switch is open and the average DC level remains fixed apart from a small drift due to the input bias current of the amplifier and switch leakage (see below). Video function In the video application, the HOLD input state will be H I GH d uri ng t he pi c t ure l i ne s w e e p a n d a negative-going sampling pulse of typically 1.2 s duration will be applied during a central portion of the Back Porch interval, so that the Back Porch or `Black' level is clamped to ground. For each line scan, this gives a brightness level consistent with that of the original camera signal, despite the AC coupling. The value of the coupling capacitor affects two main characteristics of the circuit. Firstly, the available charging current, together with the capacitor value, determines the maximum DC voltage correction which can be applied at each sample. For a charging current limit of 300 A applied for 2 s, the charge injected is Qmax = 300 A x 1.2 s = 360 pC. Then the maximum voltage shift correction is Vmax = Qmax/C = 360 pC / 0.01 F = 36 mV. Secondly, in the hold state, the voltage drift is affected as described below. Sample-hold drift In the HOLD state, the drift rate is equal to the bias/leakage current of about 1 A divided by the coupling capacitor value. For a value of 0.01 F, the drift rate is then 100 V/s. For the typical video line scan, the switch remains open for the rest of the scan duration, or about 62 s. The drift at the end of the line scan has therefore accumulated to about 6.2 mV. This will be acceptable for most applications, but if desired it can be reduced by increasing the value of the coupling capacitor. This will result in a proportionately smaller value of the maximum available correction voltage at each scan as described above. Normally, once settled, the video system requires only a very small correction at each scan, so this will not present any problem. Supply filtering & printed circuit layout In the applied circuit, the power filtering and printed layout design needs special attention as is appropriate for a high-speed analog circuit. For each supply lead, use a leadless ceramic chip capacitor placed very close to the device power pin. A value of 0.1F is recommended. In addition, a larger value capacitor, w h i ch sh o u l d b e ce r a m i c o r so l i d t a n t a l u m construction, with a value of 1 to 10 F, is also recommended for connection to each supply fairly close to the device. T h e l a y o u t n a t u r a l l y r e q u i r e s so m e sh o r t interconnections on the component side (top copper layer) and a continuous ground plane should be provided on another layer with plated via holes providing low inductance ground connections for the device and other components. The amplifier frequency response is affected to some extent by stray capacitance at the inverting input at pin 1. This effect can be minimised by providing a small cut-out area in the ground plane and other layers around pin 1, though this may not always be necessary for the application.
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002 4
ZXFV4089
PACKAGE OUTLINE PACKAGE DIMENSIONS
INCHES DIM MIN A A1 D H E L e b c 0.053 0.004 0.189 0.228 0.150 0.016 MAX 0.069 0.010 0.197 0.244 0.157 0.050 MIN 1.35 0.10 4.80 5.80 3.80 0.40 MAX 1.75 0.25 5.00 6.20 4.00 1.27 MILLIMETRES
0.050 BSC 0.013 0.008 0 0.020 0.010 8 0.020
1.27 BSC 0.33 0.19 0 0.25 0.51 0.25 8 0.50
CONTROLLING DIMENSIONS ARE IN INCHES APPROX IN MILLIMETRES
h
0.010
(c) Zetex plc 2002
Europe Zetex plc Fields New Road Chadderton Oldham, OL9 8NP United Kingdom Telephone (44) 161 622 4422 Fax: (44) 161 622 4420 uksales@zetex.com Zetex GmbH Streitfeldstrae 19 D-81673 Munchen Germany Telefon: (49) 89 45 49 49 0 Fax: (49) 89 45 49 49 49 europe.sales@zetex.com Americas Zetex Inc 700 Veterans Memorial Hwy Hauppauge, NY11788 USA Telephone: (631) 360 2222 Fax: (631) 360 8222 usa.sales@zetex.com Asia Pacific Zetex (Asia) Ltd 3701-04 Metroplaza, Tower 1 Hing Fong Road Kwai Fong Hong Kong Telephone: (852) 26100 611 Fax: (852) 24250 494 asia.sales@zetex.com
These offices are supported by agents and distributors in major countries world-wide. This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. For the latest product information, log on to
www.zetex.com
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002 5

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